A typical integrated circuit (IC) includes an IC package and a semiconductor device that is physically and electrically connected within the IC package. The semiconductor device typically includes electrostatic discharge (ESD) protection devices that protect the semiconductor device against ESD events that would otherwise cause damage. Generally, the ESD protection devices are located within the semiconductor device in close proximity to semiconductor device pads, which electrically connect to pins of the IC package.
One conventional ESD protection device provides an ESD clamp (or shunt) between the semiconductor pad to be protected and a reference conductor (i.e., a ground conductor). If power is off (e.g., when the semiconductor device is being handled prior to its installation within an IC package, or when an assembled IC is being handled prior to its installation on a circuit board), the ESD protection device shunts or clamps any positive charge on the pad that is above a particular threshold to the reference conductor. If the power is on (e.g., when the assembled IC is installed on a circuit board and is operational), the ESD protection device is deactivated and an incoming signal on the pad is permitted to pass through to other semiconductor device circuitry, i.e., internal circuits of device. An example of such an ESD protection device is described in U.S. application Ser. No. 08/979,376, entitled xe2x80x9cCross-Referenced Electrostatic Discharge Protection Systems and Methods for Power Supplies,xe2x80x9d filed Nov. 26, 1997, the entire teachings of which are incorporated herein by this reference.
Due to improvements in semiconductor technology, manufacturers can now make transistors smaller thereby reducing semiconductor-device size and power consumption. The decrease in transistor size has been accompanied by a decrease in transistor voltage tolerance, which is the voltage that can be applied safely across any two terminals of each transistor of the semiconductor device without causing damage, such as thin oxide damage in the context of MOS-type devices, for example. This maximum tolerable voltage for the transistors is commonly referred to as the rated or process technology voltage. For example, older semiconductor devices were built using a 5V process technology where each transistor could tolerate an operating voltage of 5 Volts (V) across any two terminals without sustaining thin oxide damage. More recently, semiconductor devices have been built using a 3.3V process technology. In such devices, the voltage across any two terminals of each transistor must be less than 3.3V in order to avoid causing thin oxide damage. Presently, manufacturers are implementing 2.5V and 1.5V process technologies, and such improvements in semiconductor technology are expected to continue.
Occasionally, manufacturers combine IC""s having different semiconductor technologies on the same circuit board or in the same system. For example, a manufacturer may mix some IC""s having semiconductor devices built using a 5V process technology with other IC""s having semiconductor devices built using a 3.3V process technology in order to obtain some of the benefits of using 3.3V process IC""s (e.g., smaller packaging, lower power consumption, greater speed, lower cost). For this reason, an IC containing a semiconductor device using a 3.3V process technology must often be designed to interface with IC""s containing semiconductor devices built using a 5V process technology. Specifically, the 3.3V IC must drive and receive signals at the logic levels expected by the 5V IC""s in the system. To accomplish this, the 3.3V IC often requires a 5V power supply to power the 3.3V IC""s I/O stages. Therefore, the 3.3V IC contains a mixture of 3.3V and 5V circuits.
Providing ESD protection in a mixed voltage IC tends to complicate the design of the ESD clamp and its control circuit. For example, one known semiconductor device includes a cantilevered ESD clamp and an RC-timed control circuit, which is interconnected between the power supply pad and the ESD clamp, to control deactivation of the ESD clamp. When power is off, the RC-timed circuit maintains the ESD clamp in a conductive state for a time period related to the circuit""s time constant. This allows the shunting of a short ESD event from the pad to a reference conductor. In contrast, when power is on, the RC-timed circuit operates as a voltage divider to divide a 5 V power supply signal down to a 3.6 V signal, which is used to disable the ESD clamp. Without the reduction in voltage from 5 V to 3.6 V, one or more components of the ESD clamp would be very susceptible to thin oxide damage. An example of such a circuit (hereinafter referred to as the xe2x80x9ccantilevered circuitxe2x80x9d) is described in an article entitled xe2x80x9cProtection of High Voltage Power and Programming Pins,xe2x80x9d by Maloney et al., EOS/ESD Symposium 97-246, (1997).
While having certain advantages relative to its prior art, the cantilevered circuit does suffer from certain performance problems. In particular, the cantilevered circuit is not well-suited for situations where it is desirable to disable ESD protection using a signal that is independent of the signal received on the ESD protected pad. For example, in the above-described cantilevered circuit, the 3.6 V power supply signal that disables the ESD clamp is derived from the 5 V power supply signal received on the ESD protected pad. The 3.6 V power supply signal is not independent of the 5 V power supply signal. Additionally, the RC-timed deactivation feature of the cantilevered circuit may result in inadequate ESD protection against prolonged ESD events, which are on the order of the time constant of the circuit. Furthermore, when the RC-timed circuit operates as a voltage divider during normal operation, the RC-timed circuit generates a leakage current that increases IC power consumption.
The present invention is directed to a technique for protecting a semiconductor device against ESD events that uses a control voltage that is independent of a pad. The technique involves providing the conducting path between the pad and a reference conductor that is activated and deactivated based on the limited voltage. The ESD stage provides a conducting path between the pad and a reference conductor. In particular, the technique involves providing, in response to the control voltage, a limited voltage having a magnitude that is less than a magnitude of the control voltage.
In general, according to one aspect, the invention features an electrostatic discharge protection circuit for a protected pad of a semiconductor device. The circuit is intended to protect internal circuits of the device from electrostatic discharge. The protection circuit comprises a clamping circuit that is activated to couple electrostatic charge from the protected pad and away from the internal circuits, and deactivated when the internal circuits are operational by reference to a control signal, which is derived from a high-voltage pad. A voltage limiter is also provided that reduces a magnitude of the control signal from the high-voltage pad at an active element of the clamping circuit to less than or equal to a rated voltage of the semiconductor device.
In specific embodiments, the magnitude of the control signal is greater than a magnitude of the protected pad voltage when the internal circuits are operational. For example, the high voltage pad provides power to the semiconductors I/O stages whereas the protected pad powers the core logic. Further, the voltage limiter includes at least one transistor that is interconnected between a control signal pad and the clamping circuit, preferably stacked transistors. Also, the limiter preferably includes a pull-up transistor that is interconnected between the protected pad and the clamping circuit.
In further aspects of the embodiment, the clamping circuit includes control function, specifically comprising an inverter that receives the control signal and a clamp transistor that is driven by the inverter.
In general according to another aspect, the invention features an electrostatic discharge protection method which comprises activating a clamp to couple electrostatic charge from the protected pad and away from the internal circuits in response to a control signal derived from a high-voltage pad. The clamp, however, is deactivated when the internal circuits are operational by reference to the control signal. This control signal since it comes from a high-voltage pad is reduced in magnitude at an active element of the clamping circuit to less than or equal to a rated voltage of the semiconductor device.
Finally, the invention also features a system board comprising an integrated circuit, which includes an electrostatic discharge protection circuit as described above.
The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.